In driving a liquid crystal panel by alternating driving, an active matrix liquid crystal display device, which performs dot sequential driving, precharges signal lines before supplying video signals to pixels through data signal lines. This makes it possible to charge the pixels by predetermined amounts stably. In this case, in order to adopt a driving method in which all signal lines are precharged simultaneously (hereinafter “simultaneous precharge method”), a precharge power source must have high driving capability. This is because the sum of wire capacity of all signal lines is large. To solve this problem, there is a driving method in which precharge is performed unit by unit, each unit including a small number of signal lines (hereinafter “sequential precharge method”).
For example, Patent Publication 1 (Japanese Publication for Laid-Open Patent Application, Tokukaihei 7-295520; corresponding to U.S. Pat. No. 5,686,936) discloses an arrangement in which, in outputting a video signal to one data signal line, a switch of another data signal line is turned ON by using a video-signal-sampling signal outputted from a shift register of a data signal line driver, so as to perform precharge by using a precharge power source.
Patent Publication 2 (Japanese Publication for Laid-Open Patent Application, Tokukai 2000-89194; corresponding to U.S. Pat. No. 6,731,266B1) discloses an arrangement in which all data signal lines are divided onto several blocks including data signal lines, and, in outputting video signals from a data signal line driver to data signal lines of an n-th data signal line block, data signal lines of an (n+1)-th data signal line block are precharged by a precharge power source by using video-signal-sampling signals.
Patent Publication 3 (Japanese Publication for Laid-Open Patent Application, Tokukai 2000-206491) discloses an arrangement in which a transfer pulse input of each transfer stage of a data signal line driver is used as a timing pulse for opening or closing an analog switch for precharging the data signal line of the transfer stage and also used, by being delayed from the timing pulse for precharge, as a timing pulse for opening or closing an analog switch for outputting substantive data (video signal) to the data signal line. A transfer pulse output of the transfer stage is used as a transfer pulse input of a next transfer stage, and as a timing pulse for precharge and a timing pulse for substantive data output of the next transfer stage.
In order to output video signals from these data signal line drivers to data signal lines by a dot-sequential method, each data signal line is provided with a switch having a capacitor-type control terminal (e.g. a gate) such as MOSFET including a TFT, and the switch is switched dot sequentially between conductive and nonconductive by controlling the charge voltage of the control terminal. A control signal for dot sequentially switching the switch is outputted after being shifted in a horizontal direction by a shift register generally including plural stages of flip-flops. A similar switch, which is switched dot sequentially between conductive and nonconductive so as to precharge the data signal lines, is provided separately.
According to the arrangements of the foregoing publications, a circuit for performing precharge is provided inside the data signal line driver, so that the frame of the liquid crystal display device has sufficient area, for example. As a result, the area of the precharge circuit can be reduced.
Patent Publication 4 (Japanese Publication for Laid-Open Patent Application, Tokukai 2001-135093; corresponding to U.S. Pat. No. 6,724,361B1), which is a publication for a laid-open patent application filed by the applicant of the present invention, discloses an arrangement in which a clock signal is taken onto a switch circuit upon receiving an output signal from a set-reset flip-flop of each stage of the shift register, and the clock signal is used as a set signal for a set-reset flip-flop of a next stage. Patent Publication 5 (Japanese Publication for Laid-Open Patent Application, Tokukai 2001-307495; corresponding to U.S. Pat. No. 6,724,361B1) and Patent Publication 6 (Japanese Publication for Laid-Open Patent Application, Tokukai 2000-339985), which are publications for laid-open patent applications filed by the applicant of the present invention, disclose an arrangement in which a clock signal is taken in upon receiving an output from a set-reset flip-flop of each stage of the shift register, and the clock signal is subjected to level shift and used as a set signal for a set-reset flip-flop of a next stage.
Patent Publication 7 (U.S. Patent Application Publication, No. 023461/2003), which is a publication for a laid-open patent application filed by the applicant of the present invention, discloses an arrangement of providing a precharge circuit and a shift register. While write signals are written by a write circuit onto a part of signal supply lines, the precharge circuit precharges the rest of the signal supply lines. The shift register includes a control signal supply circuit for outputting a precharge control signal, which controls conductivity (conductive or non conductive) of a second switch, to a second control terminal through a second signal line, which is separated from a first signal line for transmitting the timing pulse to a first control terminal.
However, according to the sequential precharge method of Patent Publications 1 to 3 and 7, it is impossible to supply precharge potential to source bus lines when supply of video signals to the source bus lines (hereinafter referred to as “scanning”, when appropriate) is stopped.
FIG. 27 illustrates driving waveforms in a normal scanning state (in which a video signal is supplied to each source bus line) of a display device that precharges a plurality of source bus lines by the conventional simultaneous precharge method. Here, the driving waveforms are those of three adjacent source bus lines SL1, SL2, and SL3. SSP is a start pulse of the source, SCK is a source clock signal, and PCTL is a precharge instruction signal instructing the timing for performing simultaneous precharge of the source bus lines. SMP1, SMP2, and SMP3 are sampling timing signals instructing the timing for sampling the video signals to the three adjacent source bus lines SL1 to SL3, respectively. VSL1, VSL2, and VSL3 are potentials of the source bus lines SL1 to SL3, respectively.
Operation for precharge is as follows. In time t1 to t2, the precharge instruction signal PCTL is effective (is High) and precharge potentials are supplied to the source bus lines SL1 to SL3, respectively. Then, in response to the input of the start pulse SSP (transition to High), scanning at a speed in accordance with the clock signal SCK is started, and video signals are supplied to the source bus lines SL1 to SL3 in accordance with the sampling timing signals SMP1 to SMP3, respectively.
In the simultaneous precharge method, as shown in FIG. 28, for example, in order to fix the potentials of the source bus lines to a desired potential when scanning is suspended, control is performed so that precharge is performed in accordance with the instruction signal PCTL during t7 to t8. In this way, it is possible to always supply potentials to the source bus lines. More specifically, the precharge instruction signal is High during a period from t1 to t2, which is before periods from t3 to t6 for supplying video signals to the source bus lines SL1 to SL3, and during a period from t7 to t8, which is after periods from t3 to t6 for supplying video signals. Therefore, precharge potentials are respectively supplied to the source bus lines SL1 to SL3 during the period from t1 to t2 and the period from t7 to t8. That is, during the periods in which video signals are not supplied to the source bus lines SL1 to SL3, the source bus lines SL1 to SL3 are precharged simultaneously. As a result, the potentials of the source bus lines SL1 to SL3 are always kept to be not lower than a desired potential. Thus, in the simultaneous precharge method, it is possible to supply precharge potentials to the source bus lines even when scanning is suspended.
FIG. 29 illustrates a normal scanning state of the case in which the sequential precharge method is adopted. In the sequential precharge method, precharge potentials are supplied sequentially to the source bus lines in the normal scanning state of FIG. 29.
However, in the sequential precharge method, it is impossible to supply precharge potentials to the source bus lines when scanning is suspended as in FIG. 28, for example. Therefore, in the sequential precharge method, there is a possibility that a precharge potential is supplied to a source bus line only for a very short period, making it impossible to charge the source bus line sufficiently.
Patent Publication 4 to 6 have no disclosure or suggestion concerning precharge.